Embedded Software-Based Self-Test for Programmable Core-Based Designs

At-speed testing of high-speed circuits is becoming increasingly difficult with external testers. Therefore, empowering the chip to test itself seems like a natural solution. Hardware-based selftesting techniques have limitations due to performance and area overhead as well as problems caused by application of non-functional patterns. Another possible solution is software-based self-testing where the programmable cores are used for on-chip test generation, measurement, response analysis and even diagnosis. After the programmable core has been self-tested, it is reused for testing onchip buses, interfaces and other non-programmable cores. The advantages of this methodology include at-speed testing, low design-for-testability overhead and application of functional patterns. Embedded Software-Based Self-Test for Programmable CoreBased Designs A. Krstic L. Chen W.-C. Lai K.-T. Cheng S. Dey * Department of ECE, University of California, Santa Barbara, CA 93106 # Department of ECE, University of California, San Diego, CA 92093 Abstract At-speed testing of high-speed circuits is becoming increasingly difficult with external testers. Therefore, empowering the chip to test itself seems like a natural solution. Hardware-based selftesting techniques have limitations due to performance and area overhead as well as problems caused by application of non-functional patterns. Another possible solution is software-based self-testing where the programmable cores are used for on-chip test generation, measurement, response analysis and even diagnosis. After the programmable core has been self-tested, it is reused for testing onchip buses, interfaces and other non-programmable cores. The advantages of this methodology include at-speed testing, low design-for-testability overhead and application of functional patterns.